AMD launches Instinct MI450X with 288 GB of HBM4 and 40 PFLOPs of FP4
AMD has added a third GPU to its Instinct MI400 Series. The AMD Instinct MI450X, introduced on November 12, 2026, carries 288 GB of HBM4 per GPU and keeps the compute, memory bandwidth and interconnect of the flagship MI455X, including a peak of 40.3 PFLOPs of OCP MXFP4 compute and 23.3 TB/s of memory bandwidth. The only headline difference between the two parts is memory capacity: the MI455X has 432 GB of HBM4, so the MI450X gives up 144 GB, one third of the flagship's memory, while keeping the same silicon throughput.
The announcement came in a release titled "AMD Advances the Instinct MI400 Series for AI and Scientific Computing," which also added detail on the MI430X, the series member built for high-precision scientific computing, and published a new measured inference result for the MI455X running in AMD's Helios rack-scale system. AMD says the MI455X reached 21,333 tokens per second per GPU on DeepSeek-R1 in an MLPerf Inference Offline configuration, which the company describes as up to 30% higher throughput than the latest published MLPerf offline result for NVIDIA's Vera Rubin NVL72.
The MI450X is designed for the same Helios rack as the MI455X, and AMD frames the choice between them as a question of workload size. The company positions the MI450X for models and serving patterns that fit within 288 GB per GPU, where operators want to meet throughput and response-time targets while keeping operating expenses down, and it keeps the MI455X as the option for larger models, longer contexts or higher concurrency. AMD lists the MI450X launch date as November 12, 2026, on the product's specification page, and it has not published a price or a shipping date for the new part.
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AMD INSTINCT MI450X SPECIFICATIONS AND ARCHITECTURE.
The MI450X is built on AMD's CDNA 5 architecture and, according to AMD's specification page, uses TSMC 2 nm and 3 nm process technology with 320 billion transistors, 256 work group processors and a peak engine clock of 2,400 MHz. Memory is arranged as eight stacks of HBM4 for a total of 288 GB, backed by 192 MB of L2 cache, and the peak memory bandwidth is the same 23.3 TB/s that AMD quotes for the MI455X.
The compute figures are identical to the flagship's. AMD lists 40.3 PFLOPs of peak OCP MXFP4, 20.1 PFLOPs of MXFP6 and FP8, and 5 PFLOPs of FP16 and BF16 matrix throughput, rising to 10.1 PFLOPs with structured sparsity. Vector FP16 and FP32 are listed at 315 TFLOPs, while FP64 vector and matrix performance is 5 TFLOPs, which shows that this part is tuned for low-precision AI work rather than double-precision simulation.
For connectivity, the MI450X offers 3.6 TB/s of bidirectional scale-up bandwidth over UALink over Ethernet (UALoE) and 600 GB/s of bidirectional scale-out bandwidth over UALink, again matching the MI455X. The GPU ships in AMD's Enhanced Accelerator Module form factor with direct liquid cooling, supports SR-IOV virtualization and ECC memory, and runs on the ROCm stack with support for PyTorch, JAX, TensorFlow, ONNX Runtime, SGLang, Triton and the Kokkos and RAJA HPC libraries.
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Specification | Instinct MI450X |
Architecture | CDNA 5 |
Process | TSMC 2 nm and 3 nm |
Transistors | 320 billion |
HBM4 memory | 288 GB (8 stacks) |
Peak memory bandwidth | 23.3 TB/s |
Peak FP4 (OCP MXFP4) | 40.3 PFLOPs |
Peak FP8 | 20.1 PFLOPs |
Peak FP16/BF16 matrix | 5 PFLOPs (10.1 with sparsity) |
Peak FP64 | 5 TFLOPs |
Scale-up bandwidth | 3.6 TB/s (UALoE) |
Scale-out bandwidth | 600 GB/s (UALink) |
Cooling | Direct liquid cooling |
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AMD has not listed a total board power for the MI450X on its specification page, so there is no official basis yet for comparing performance per watt with the MI455X or with competing GPUs.
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INSTINCT MI450X VS MI455X VS MI430X: HOW THE MI400 SERIES IS SPLIT.
With the MI450X in place, the MI400 Series now covers three distinct roles. The MI455X is the frontier AI part with the most memory, the MI450X is the same AI engine with a smaller memory footprint, and the MI430X is the scientific computing variant with native high-throughput FP64. AMD's MI400 Series page lists 288 TFLOPs of hardware FP64 for the MI430X, compared with 5 TFLOPs on the MI450X, and gives the MI430X the same 432 GB of HBM4 as the MI455X with up to 23.3 TB/s of bandwidth.
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Model | HBM4 | Bandwidth | Peak FP4 | Peak FP64 | Main role |
Instinct MI455X | 432 GB | 23.3 TB/s | 40 PFLOPs | Not listed | Large-model AI training and inference |
Instinct MI450X | 288 GB | 23.3 TB/s | 40.3 PFLOPs | 5 TFLOPs | AI inference within 288 GB per GPU |
Instinct MI430X | 432 GB | 23.3 TB/s | Not listed | 288 TFLOPs | HPC, sovereign AI, AI for science |
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AMD's MI400 page states that Helios volume deployments with the MI455X are expected in the second half of 2026 and that the MI430X is expected in 2027. The MI430X is already tied to named systems: AMD lists the upcoming Discovery supercomputer at the U.S. Department of Energy's Oak Ridge National Laboratory and the European Alice Recoque and Herder systems as planned deployments.
The release also refers to new AMD research covering 47 workload configurations across 11 applications and benchmarks, which examined where FP64 emulation on low-precision hardware can work and where scientific codes still depend on native double precision. AMD did not publish the findings in the release itself, and says only that they support its decision to keep a dedicated high-precision part in the lineup.
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AMD HELIOS RACK WITH MI450X OR MI455X: MEMORY AND COMPUTE PER RACK.
Helios is AMD's rack-scale reference design for OEM and ODM partners, combining 72 Instinct GPUs with EPYC CPUs and Pensando networking. AMD's figures for a Helios rack with MI455X GPUs are 31 TB of HBM4, up to 2.9 exaFLOPs of MXFP4, up to 1.4 exaFLOPs of MXFP8 and about 1.7 PB/s of aggregate memory bandwidth.
Because the MI450X shares the MI455X's compute and bandwidth, a Helios rack filled with MI450X parts keeps the same compute and bandwidth totals and changes only the memory pool. Multiplying AMD's per-GPU figures by 72 gives about 20.7 TB of HBM4 per rack with the MI450X, against 31.1 TB with the MI455X, while peak MXFP4 stays at about 2.9 exaFLOPs in both cases. AMD says customers can choose either GPU on the same open rack architecture and the same ROCm software base.
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Helios rack (72 GPUs) | With MI455X | With MI450X |
Total HBM4 | 31.1 TB | 20.7 TB |
Peak MXFP4 | about 2.9 exaFLOPs | about 2.9 exaFLOPs |
Aggregate memory bandwidth | about 1.68 PB/s | about 1.68 PB/s |
Software | ROCm | ROCm |
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The rack totals for the MI450X configuration are Data Studios calculations from AMD's per-GPU specifications; AMD's release does not publish a separate rack sheet for MI450X-based Helios systems.
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INSTINCT MI450X VS NVIDIA VERA RUBIN: OFFICIAL SPECIFICATIONS COMPARED.
The 288 GB capacity puts the MI450X level with NVIDIA's Rubin GPU on memory, since NVIDIA's official Vera Rubin NVL72 page also lists 288 GB of HBM4 per GPU and 20.7 TB per 72-GPU rack. On the other published figures, AMD's peak numbers are higher. NVIDIA lists 19.2 TB/s of memory bandwidth per Rubin GPU, against 23.3 TB/s for the MI450X, a difference of about 21% that is consistent with AMD's claim of up to 20% higher HBM bandwidth for its Helios GPUs.
Compute comparisons need care because the two companies quote different formats. NVIDIA lists 35 PFLOPs of dense NVFP4 for training and 50 PFLOPs of NVFP4 for inference with sparsity, while AMD's 40.3 PFLOPs refers to dense OCP MXFP4. Comparing dense with dense, the MI450X's peak FP4 figure is about 15% above Rubin's, its FP8 figure of 20.1 PFLOPs is about 15% above Rubin's 17.5 PFLOPs, and its 5 PFLOPs of dense BF16 compares with 4 PFLOPs for Rubin.
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Per-GPU specification | AMD Instinct MI450X | NVIDIA Rubin (Vera Rubin NVL72) |
HBM4 memory | 288 GB | 288 GB |
Memory bandwidth | 23.3 TB/s | 19.2 TB/s |
Dense FP4 | 40.3 PFLOPs (MXFP4) | 35 PFLOPs (NVFP4) |
Dense FP8 | 20.1 PFLOPs | 17.5 PFLOPs |
Dense FP16/BF16 | 5 PFLOPs | 4 PFLOPs |
FP64 | 5 TFLOPs | 33 TFLOPs |
Scale-up bandwidth | 3.6 TB/s | 3 TB/s (NVLink) |
Rack HBM4 (72 GPUs) | 20.7 TB | 20.7 TB |
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These are peak theoretical figures published by each vendor, and MXFP4 and NVFP4 are different 4-bit formats with different scaling schemes, so the table describes hardware ceilings rather than measured application speed. The FP64 row runs the other way: Rubin's 33 TFLOPs is well above the MI450X's 5 TFLOPs, and AMD's answer for double-precision work is the MI430X, whose 288 TFLOPs is about 8.7 times Rubin's figure, matching the 8.7x projection in AMD's own materials.
The one measured comparison in the release concerns the MI455X. AMD Performance Labs tested it in October 2026 on Helios and recorded 21,333 tokens per second per GPU on DeepSeek-R1 in an MLPerf Inference Offline setup, comparing the result with NVIDIA's Vera Rubin NVL72 entry 6.1-0106 in the MLPerf Inference v6.1 Closed Division. AMD describes its own run as an AMD-tested configuration, and the release does not state precision or batch settings, so the 30% figure should be read as a vendor claim until comparable results appear in an MLCommons submission.
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WHAT THE MI450X CHANGES FOR AI INFRASTRUCTURE BUYERS AND DEVELOPERS.
For operators planning Helios deployments, the MI450X turns memory capacity into a separate purchasing decision. A serving cluster for models whose weights and key-value cache fit comfortably in 288 GB per GPU gets the full compute and bandwidth of AMD's flagship without paying for 432 GB of HBM4 on every card, which AMD links directly to lower operating expenses. AMD has not published prices for either GPU, so the size of any saving is not yet known.
A rough sizing exercise shows where the line falls. At 4-bit precision, the weights of a 70-billion-parameter model take about 35 GB, which leaves most of a single MI450X free for key-value cache and batching. A 405-billion-parameter model stored in FP8 needs about 405 GB for weights alone, which exceeds one MI450X but fits on a single MI455X, while a one-trillion-parameter model in 4-bit form needs about 500 GB and must be split across GPUs in either case. These weights-only figures leave out key-value cache and runtime overhead, which grow with context length and concurrency and are the reasons AMD gives for choosing the MI455X for long-context and high-concurrency serving.
For developers, nothing changes at the software layer. The MI450X runs the same ROCm stack and framework support as the MI455X, so code and serving configurations written for one should move to the other with memory limits as the main adjustment. Teams already testing AMD hardware for inference, such as the setup described in our report on AMD Instinct Coder 355 serving 85 developers on MI355X GPUs, would be working with the same ROCm base on the new generation. Buyers comparing platforms will also be looking at NVIDIA's large Rubin commitments, such as the $40 billion Apollo lease for Vera Rubin GPUs tied to Grok.
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Question | What AMD has published |
Launch date | November 12, 2026 |
Price | Not disclosed |
Board power | Not disclosed |
Shipping date for MI450X | Not disclosed |
Helios volume deployments | Expected 2H 2026 |
MI430X availability | Expected 2027 |
Software | ROCm, same as MI455X |
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AMD INSTINCT MI450X: CONFIRMED SPECIFICATIONS AND OPEN QUESTIONS.
The confirmed facts are specific. The MI450X is a CDNA 5 GPU with 288 GB of HBM4, 23.3 TB/s of bandwidth, 40.3 PFLOPs of peak MXFP4 and the same 3.6 TB/s scale-up link as the MI455X, and it slots into the same 72-GPU Helios rack on the same ROCm software. On paper it matches NVIDIA's Rubin on memory capacity and exceeds it on peak low-precision compute and memory bandwidth, while trailing it on FP64.
Several points that decide real purchases remain open. AMD has not disclosed board power, pricing or a shipping date for the MI450X, it has not named customers for the new part, and its strongest performance claim, the 30% MLPerf advantage, refers to the MI455X and rests on AMD's own test configuration. Independent MLPerf submissions for MI400 Series hardware, and the first OEM rack configurations built on the MI450X, will show whether the trimmed-memory design delivers the cost advantage AMD describes for inference fleets.
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