Google unveils TPU 8i Max with 2x TPU 8i compute and confidential TPU 8tx

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Google has added two new systems to its eighth-generation Tensor Processing Unit family. TPU 8i Max places two TPU 8i chips on a single package and, according to Google, doubles the compute, on-chip SRAM and HBM bandwidth of TPU 8i, while TPU 8tx reuses the TPU 8t chip with 5th Generation AMD EPYC host processors and hardware-level isolation for confidential inference. Amin Vahdat, Google's SVP and Chief Technologist for AI and Infrastructure, announced both systems on November 9, 2026, in a post published on Google's company blog and cross-posted to the Google Cloud blog.

The two additions bring the eighth generation to four systems. TPU 8t, built for large-scale training, and TPU 8i, built for low-latency inference, were announced at Google Cloud Next in April. Google says this is the first time it has introduced four TPU systems in a single year, and it positions the new pair around two workloads that the original split between training and inference did not fully cover: inference over very long contexts, such as agents working across an entire codebase or hours of video, and inference or fine-tuning on data that regulated companies and governments cannot expose to the platform operator.

Google did not publish prices, availability dates, regions or absolute per-chip figures for either new system. Every number it did publish is relative, expressed as a multiple of TPU 8i or TPU 8t, so the absolute values below are derived from the specifications Google released for those two chips in April and are labelled as such.

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TPU 8I MAX: TWO TPU 8I CHIPS IN ONE PACKAGE FOR LONG-CONTEXT INFERENCE.

TPU 8i Max is a dual-chip package. Google says compute, SRAM and HBM bandwidth all scale "in lockstep" to twice the level of a single TPU 8i, and that the package fits twice the silicon into the existing rack footprint. The company describes it as the system with the highest compute density per rack in the eighth-generation lineup, with more compute per square foot and per watt of data center space.

The base chip explains the design choice. In its April technical deep dive, Google listed TPU 8i with 10.1 petaflops of peak FP4 compute, 288 GB of HBM, 8,601 GB/s of HBM bandwidth and 384 MB of on-chip SRAM, three times the SRAM of the previous generation. Large SRAM and high memory bandwidth are the resources that limit decoding speed when a model has to read a very large key-value cache for every generated token, which is the situation Google describes for long-context agent workloads. Doubling bandwidth and SRAM per package targets that bottleneck directly.

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Specification	TPU 8i (official, April 2026)	TPU 8i Max (2x as stated by Google)
Chips per package	1	2
Peak FP4 compute	10.1 PFLOPS	20.2 PFLOPS (derived)
HBM bandwidth	8,601 GB/s	17,202 GB/s (derived)
On-chip SRAM	384 MB	768 MB (derived)
HBM capacity	288 GB	Not stated by Google
Rack density	Baseline	2x silicon in the same footprint

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The derived column multiplies Google's official TPU 8i figures by the factor of two that Google gives for compute, SRAM and HBM bandwidth. Google did not list HBM capacity among the doubled resources. Two TPU 8i chips would carry 576 GB between them if each kept its 288 GB, but the company has not confirmed the package's memory capacity, and that figure should not be treated as a specification until Google publishes one.

Google also did not say whether TPU 8i Max uses the same Boardfly pod topology as TPU 8i. In April, Google described Boardfly as a design that links four-chip rings into fully connected groups of eight boards and joins 36 groups through optical circuit switches, cutting the maximum distance between any two chips in a 1,024-chip configuration from 16 hops on a 3D torus to 7.

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TPU 8TX: CONFIDENTIAL INFERENCE ON TPU 8T SILICON WITH AMD EPYC HOSTS.

TPU 8tx is built on the same silicon as TPU 8t, the training chip, and pairs it with 5th Generation AMD EPYC CPU hosts. That host choice is a departure from TPU 8t and TPU 8i, which Google introduced in April as the first TPUs to run on its own Arm-based Axion CPUs. Google says TPU 8tx adds hardware-level security that keeps sensitive data and model weights protected and isolated while in use, which is the definition of confidential computing: protection during processing in addition to encryption at rest and in transit.

Google says TPU 8tx also uses the Boardfly network from TPU 8i, giving it up to 2x lower latency than TPU 8t with what the company calls a near-zero performance penalty for the security features. The intended customers are regulated enterprises and governments. Google lists three workloads that can run on one system without moving sensitive data between clusters: fine-tuning on private data, distilling large models into smaller ones, and reinforcement learning for agents. It also describes TPU 8tx as suited to small-scale training.

Because TPU 8tx uses TPU 8t silicon, the April figures for that chip give the closest available reference: 12.6 petaflops of peak FP4 compute, 216 GB of HBM, 6,528 GB/s of HBM bandwidth and 128 MB of on-chip SRAM. Google has not published separate figures for TPU 8tx, and it has not said whether the confidential-computing mode affects usable memory or throughput beyond the "near-zero" penalty it claims. The post also gives no detail on the trusted execution environment, the attestation process customers would use to verify the isolation, or which AMD security technologies the EPYC hosts contribute.

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GOOGLE'S EIGHTH-GENERATION TPU LINEUP COMPARED: 8T, 8I, 8TX AND 8I MAX.

With four systems, the eighth generation now separates training, standard inference, dense long-context inference and confidential workloads into distinct products. The table summarizes what Google has published for each, using only official figures and stating where a value is derived or absent.

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System	Role stated by Google	Silicon	CPU host	Network	Key official figures
TPU 8t	Large-scale training	TPU 8t	Axion (Arm)	3D torus, 9,600-chip superpod	12.6 PFLOPS FP4, 216 GB HBM, up to 2.7x training price-performance vs previous generation
TPU 8i	Low-latency inference	TPU 8i	Axion (Arm)	Boardfly, up to 1,024 active chips per pod	10.1 PFLOPS FP4, 288 GB HBM, up to 80% better inference price-performance
TPU 8tx	Confidential inference, private fine-tuning, small-scale training	TPU 8t	5th Gen AMD EPYC	Boardfly	Up to 2x lower latency than TPU 8t; per-chip figures not published
TPU 8i Max	Long-context inference, maximum rack density	Two TPU 8i chips	Not stated	Not stated	2x TPU 8i compute, SRAM and HBM bandwidth

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Google's efficiency claims for the generation remain the April ones: up to 2x better performance per watt than Ironwood, the seventh-generation TPU, for both TPU 8t and TPU 8i, along with fourth-generation liquid cooling. The new post adds no efficiency figures for TPU 8tx or TPU 8i Max beyond the statement that TPU 8i Max delivers more compute per watt of rack space.

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TPU SOFTWARE STACK: TORCHTPU, TPU SYNC, CLOUD PATHWAYS AND GKE DYNAMIC SLICING.

Google paired the hardware announcement with several software releases aimed at teams that build on PyTorch and GPU-oriented serving stacks. TorchTPU, which Google says it open-sourced last month, lets native PyTorch code and Hugging Face models run on TPUs without rewrites, and it ships with TPU backends for the vLLM and SGLang inference engines. A TPU agent suite, open source and in preview, plugs into Claude Code, Cursor and Google Antigravity to automate onboarding, diagnose performance bottlenecks and autotune kernels.

For serving, Google released the open-source XLA Serving Engine, which lets developers train in Python and serve from a low-latency C++ runtime across TPUs, GPUs and CPUs. TPU Sync, also open source, treats HBM, host DRAM, shared storage and the network as one memory hierarchy and moves key-value caches off-chip in milliseconds. Google says it cuts KV transfer latency and time to first token by more than 90%, a vendor figure for which the post gives no test configuration. Agent Compute Engine suspends idle agent sessions and resumes them automatically, which Google presents as a way to stop paying for accelerators while an agent waits on a tool call or a user.

Two orchestration features moved to general availability on Google Kubernetes Engine. Cloud Pathways provides single-controller orchestration of multi-slice TPU systems through the pathwaysutils library, with colocated Python sidecars, slice hot-swapping in under a minute and elastic resharding; Google says it is built on the same runtime that Google DeepMind uses for Gemini. GKE dynamic slicing uses optical circuit switching to combine TPU cubes into larger topologies or split them into smaller ones, and Google claims up to 5x faster job startup and up to 4.5x faster fault recovery.

Google also says its native vLLM and TorchTPU stack reached state-of-the-art price-performance on the InferenceX and AgentX benchmarks run by SemiAnalysis. The post links the evaluations but does not reproduce any figures, so the claim cannot be checked against competing GPU systems from the announcement alone.

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TPU 8TX AND TPU 8I MAX AVAILABILITY, PRICING AND WHO CAN USE THEM.

Google has not announced when TPU 8tx or TPU 8i Max will be offered to Google Cloud customers, in which regions, or at what price. The announcement contains no preview program, no interest form specific to the new systems and no machine-type names. For TPU 8t and TPU 8i, Google said in April that both chips would be generally available later in 2026 and directed customers to an interest form; the November post does not update that timeline either.

The practical audience differs by system. TPU 8i Max is aimed at teams serving models with very large context windows, where memory bandwidth and SRAM per rack determine how many concurrent long sessions a cluster can hold. TPU 8tx is aimed at organizations whose compliance rules prevent them from sending model weights or customer data to shared accelerators, such as banks, healthcare providers and public agencies, and that want fine-tuning, distillation and reinforcement learning on the same isolated system. Teams already running PyTorch workloads on GPUs are the target of TorchTPU and the TPU agent suite, both of which can be tried today because they are open source.

Google says it now has nearly 100 TPU customers, including frontier labs, trading firms, retailers and universities, and that TPUs also run inside customers' own data centers. Google has been placing TPU capacity with outside companies, as in Oracle's plan to bring Google TPUs into Oracle Cloud Infrastructure, and it has explored more unusual deployments such as Project Suncatcher's TPUs in orbit. Google added that it uses AlphaChip reinforcement learning and Gemini to generate chip layouts in hours instead of weeks.

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TPU 8I MAX AND TPU 8TX: CONFIRMED FACTS AND OPEN QUESTIONS.

Google has confirmed the architecture of both systems at a high level. TPU 8i Max is two TPU 8i chips in one package with twice the compute, SRAM and HBM bandwidth of TPU 8i and twice the silicon per rack. TPU 8tx is TPU 8t silicon on 5th Generation AMD EPYC hosts with hardware isolation of data and weights in use, Boardfly networking and up to 2x lower latency than TPU 8t. The software releases are concrete and, in the case of TorchTPU, TPU Sync, the XLA Serving Engine and the agent suite, open source; Cloud Pathways and GKE dynamic slicing are generally available.

The missing pieces are the ones buyers need for planning. Google has published no absolute specifications for either new system, no HBM capacity for TPU 8i Max, no technical description of the TPU 8tx trusted execution environment or attestation, no benchmark figures for the InferenceX and AgentX claims, and no prices, regions or dates. Until those appear in Google Cloud documentation, TPU 8i Max is best read as twice a TPU 8i on the three resources Google named, and TPU 8tx as a TPU 8t system rebuilt around AMD hosts for confidential workloads.

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